
General Purpose Power Supply (GPDPS) 6 Device PowerSupply
System Reference, January 2001
167
Sample IDDQ Current Settling Time
The table below shows the settling time required for static
IDDQ current measurements (sample IDDQ only). The
load step appearing when halting the clock, has to be regu-
lated by the DPS. It results in a current flowing through
the measurement shunts into the DUT bypass capacitor.
The minimum settling time depends on the load and test
situation and should be evaluated on a case by case basis.
Table 32 Sample IDDQ Current Settling Time
In related test functions, the wait times are automatically
set (there is no need to specify them explicitly).
Capacitor Current Settling Time
100 nF ∼ 3 ... 6 ms
4 µF ∼ 5 ... 8 ms
20 µF ∼ 5 ... 8 ms
100 µF ∼ 5 ... 8 ms
Komentáře k této Příručce