AWG G3 PAD FOR PS3 Specifikace Strana 282
- Strana / 285
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Index
System Reference, January 2001
269
Index
#
128 pins modules 38
50 Ohm impedance 118
A
AC/DC Converters 28
Active load 122
Adjusting synchronization timing
249
Alternative master clock
generator 50
AMC 50
Analog clock domain 49
analog dominant configurtation
74
analog instruments
fill order 81
analog dominant 83
digital dominant 81
instrument count
analog dominant 85
digital dominant 83
list 80
pogo pad assignment 88
AWG 90
digitizers 91
TIAs 92
sampler 82, 85
time interval analyser 82, 84
wafe form generater 82
Analog modules 183
Master trigger function 260
Synchronization 242
Trigger input pins 248
analog modules 59
specifications 71
arbitrary wafe form generater
pogo pad assignment 90
Arbitrary Waveform Generator
184
AWG 184
Functions 184
pogo pad assignment 90
Specifications 184
B
Bidirectional pins 121
C
cage numbering 64
card cage numbering 64
card cages 59, 60
allocation 63
1024 pin DUT board 65
512 pin DUT board 64
Cardcages 38
Channel Boards 41
Characteristic Impedance 129
Chiller Unit 29
Clock Board 43, 44
Clock board 49
Clock domain 49
CMOS outputs 121
Components 23, 37
configuration 70
analog dominant 74
digital dominant 71
Cooling system 28
Cooling Unit 29
Crosstalk 118, 131
Current measurement 139, 164, 178
Connect Time 164
Device operation sequence 164
Device stop 164
with DPS 164
D
DC/DC Boards 42
Device Power Supply 135, 168, 181
GPDPS 136
HCDPS 168
HVDPS 181
device power supply
GPDPS 86, 94
HVDPS 86, 94
pogo pad assignment 93
Diagnostics 30
digital boards 59
Digital clock domain 49
digital dominant configuration 71
Digitizer 203
digitizers
pogo pad assignment 91
Disconnecting DPS 162
Docking 25
DPS
Current measurement 164
Connect time 164
Device operation sequence
164
Device stop 164
IDDQ Settling Time 167
Disconnecting 162
High Impedance Mode 162
Low Impedance Mode 162
DPS Board 40
Dual High Speed Sampler 216
Analog-to-Digital Converter
223
Channel Multiplexer 223
Clock Distributor 223
Input Multiplexer 220
Sampler Unit 223
Sequencer 224
Specifications 218
Timing Generator 223
Waveform Memory 224
Dummy Pads 116
DUT board
Design 57, 115
Design for mixed-signal tests
124
DUT board options 62
DUT boards
pad blocks 67
E
Emergency Off 36
- System Reference 1
- Objectives of this Manual 3
- Audience 3
- Scope of the Manual 3
- Safety Information 4
- 2 System Startup 31 6
- 3 Hardware Components 37 6
- 6 Device PowerSupply 135 7
- 7 Analog Modules 183 8
- A XICOR EEPROM Summary 267 9
- Index 269 9
- Table of Contents 10
- List Of Figures 11
- System Overview 15
- Revision History 16
- System Characterization 18
- Technical Highlights 20
- AC/DC Converters 21
- (in support rack) 21
- Major Components 23
- (as shown here) 24
- DUT Interface 25
- The Manipulator 26
- ON/OFF Unit 27
- The Cooling System 28
- The Workstation 29
- System Startup 31
- Emergency OFF 32
- Standby (red) 32
- ON (green) 32
- Running the System Software 34
- Emergency Off 36
- Hardware Components 37
- Tester Electronics 38
- 128 pins 39
- DPS Channel 1 40
- DPS Channel 2 40
- DPS Channel 3 40
- DPS Channel 4 40
- Channel Board 42
- Master Clock Generator 43
- ReferenceVoltage 43
- Generator 43
- High Precision PMU 43
- Parametric Measurement Units 45
- Pin PMU Settling Time 46
- Time for converting a 46
- High-Precision PMU 47
- Master Clock System 49
- 512-Pin Testhead 53
- Analog Clock Domain 54
- Overview of Test Heads 59
- Structure of Card Cages 60
- DUT Board Mechanical 61
- Overview of DUT Board Options 62
- Allocation of Card Cages 63
- Pad Blocks 67
- Testhead 69
- Test System Configuration 70
- Analog Dominant Configuration 74
- Overview of Filling 78
- Digital Fill Order 79
- (under investigation) 80
- Analog Fill Order 81
- DPS-Type Fill Order 86
- Pogo Pad Assignment 88
- Analog Pogo Pad Location 89
- Orientation Marker 95
- on Housing 95
- Utility, EEPROM and HPMU 97
- Possible Positions 102
- for the EEPROM 102
- Wafer Prober DUT Board and 104
- Probe Card 104
- DUT Board of Wafer Prober 105
- Seg. = Segment 107
- (Group) No. in 113
- DUT Board Performance 115
- Considerations 115
- Signal Traces 116
- Keep-out Areas 117
- Maintaining Signal Fidelity 118
- Signal Inhomogeneities 119
- Correctly Terminating Signal 120
- Terminating Output Pins 121
- Termination Checklist 122
- Reducing I/O Round-Trip Times 123
- DUT Board Design for Mixed 124
- Signal Tests 124
- Analog Ground 126
- (Ground Plane) 126
- Digital Ground 126
- Printed Circuit Board 129
- Sharp Corner 131
- Rounded Corner 131
- Device PowerSupply 135
- General Purpose Power Supply 136
- Switching DPS Voltages 138
- Ganged GPDPS Channels 138
- GPDPS Specifications 139
- Supply Voltage 140
- Supply Current 140
- Setting up Performance Ranges 141
- 20 mA –> 0 151
- 0 –> 20 mA 151
- Decoupling Recommendations 154
- Voltage Settling Times 157
- DPS channel switching into 158
- Ganging GPDPS Channels 159
- Disconnecting the DPS 162
- Routing DPS Lines 163
- Device Operation Sequence 164
- High Current Power Supply 168
- Connection to DUT Board 169
- Block Diagram 170
- HCDPS Specifications 176
- Ganging HCDPS Boards 177
- Disconnecting the HCDPS 177
- Routing HCDPS Lines 177
- HVDPS General Description 181
- HVDPS Specifications 182
- Analog Modules 183
- Waveform Generators 184
- Downloading 185
- Controlling 185
- Outputting 185
- Output Order 185
- High Speed AWGs 189
- Output Multiplexer 190
- SYNC CLK 191
- SYNC DATA 191
- Output Amplifier 193
- Attenuator 194
- Digital-to-Analog Converter 194
- Timing Generator 194
- Sequencer and Waveform Memory 195
- Front-end Module 196
- Attenuator/ 197
- AWG Instrument 201
- Waveform Digitizers 203
- Synchronization trigger 204
- Digitizing then memorizing 204
- Sampling Period 204
- Initial Discard 204
- Analog Out 205
- Synchronization 205
- Input Multiplexer 209
- Figure 93 Input Resistance 210
- Input Amplifier 214
- Analog-to-Digital Converter 214
- Sampler Overview 216
- Theory of Operation 219
- DC offset 221
- Time Interval Analyzer 225
- Single Channel 226
- Dual Channel 226
- TrigDelayCnt 228
- PW+(PW ) 228
- PD++ (PD +, PD+ ,PD ) 229
- TIA Key Specifications 233
- Input Block 238
- TIA Instrument 240
- ± the fixed 243
- Trigger signal 244
- @trigger input pin 244
- Analog module’s start timing 244
- @Analog module pin 244
- Synchronization Trigger 248
- Measurement start 249
- @DUT pin 249
- Analog signal 249
- Trigger edge setting 249
- Trigger Line, and Signal Line 250
- Synchronization Uncertainty 254
- Beginning of 258
- Tester Period 258
- Master Trigger Function 260
- Master-Slave” 261
- Appendices 265
- 266 Test Setup, January 2001 266
- XICOR EEPROM Summary 267
- NOT RECOMMENDED 268
- FOR NEW DESIGNS 268
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