
Sampler 7 Analog Modules
System Reference, January 2001
217
In the sampler, the sampling period (T) is slightly different
(∆t) from a multiple of the signal period (t), that is,
T=nt+∆t. (∆t is called the equivalent sampling period.)
This under-sampling technique is called Coherent
Sampling. The sampling is performed for each of the spec-
ified phase points on the measured signal, then repeated
and averaged for each phase point.
To obtain a very short equivalent sampling period (∆t), the
sampling period (T) must be freely set. In this case, the
coherent sampling should use two master clocks. Two
master clocks are used, one for both the DUT (input signal
to sampler) and the synchronization trigger to the sampler
and one for the sampling clock of the sampler.
The shortest equivalent sampling period for using two
master clocks is 1 ps.
The following figure illustrates coherent sampling with
two master clocks:
Figure97 Coherent Sampling
T
T
T
t
t
t t
nt + t (n =2)
smp_ov
Phase Lock
Master Clock of
Digital Clock Domain
Master Clock of
Analog Clock Domain
I/O Channel Board
Sampler
DUT
Clock
Analog Out
Synchronization
Trigger
Sample
I/O Channel Board
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